Japanese Patent Application No. 2001-165450 filed on May 31, 2001, is hereby incorporated by reference in its entirety.
The present invention relates to a nonvolatile semiconductor memory device including memory cells, each having two nonvolatile memory elements controlled by one word gate and two control gates.
As one type of nonvolatile semiconductor memory device, a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor or Substrate) device is known. In the MONOS nonvolatile semiconductor memory device, a gate insulating layer between a channel and a gate is formed of a laminate consisting of a silicon oxide film, silicon nitride film, and silicon oxide film. Charges are trapped in the silicon nitride film.
The MONOS nonvolatile semiconductor memory device is disclosed in literature (Y. Hayashi, et al., 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123). This literature discloses a twin MONOS flash memory cell including two nonvolatile memory elements (MONOS memory cells) controlled by one word gate and two control gates. Specifically, one flash memory cell has two charge trap sites.
In order to drive the twin MONOS flash memory cell, two bit lines, one word line, and two control gate lines are necessary.
Of these interconnects, two bit lines and two control gate lines are generally wired along the column direction. However, it is difficult to provide four interconnects (two bit lines and two control gate lines) within the width of a plurality of memory cells in one column using the same metal interconnect layer even in the case of using a photolithographic process with a minimum line and space width.
Therefore, the wiring space must be secured by increasing the width of the memory cells in one column. However, this causes a decrease in the degree of integration of the memory cells, whereby it is impossible to deal with a recent increase in the capacity of the nonvolatile semiconductor memory device.
The present invention may provide a highly integrated nonvolatile semiconductor memory device in which one memory cell has two trap sites.
The present invention may also provide a nonvolatile semiconductor memory device in which memory cells are highly integrated by reducing the pitch of control gate lines and bit lines.
The present invention may also provide a nonvolatile semiconductor memory device capable of securing the degree of margin and freedom relating to the arrangement of interconnects for supplying electric power to the control gates and bit lines.
According to one aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a memory cell array region in which a plurality of memory cells are arranged in first and second directions intersecting each other, each of the memory cells having two nonvolatile memory elements and being controlled by one word gate and two control gates.
The memory cell array region includes: a plurality of control gate lines which connects in the first direction the control gates in each column of the memory cells disposed in the first direction; and sub control gate lines extending in the first direction in an upper layer of the control gate lines, the number of the sub control gate lines being half the number of the control gate lines.
Each of the sub control gate lines is connected to adjacent two of the control gate lines in adjacent two of the memory cells in the second direction. Since the number of the sub control gate lines is substantially half the number of the control gate lines, the degrees of margin and freedom relating to arrangement of the sub control gate lines are increased.
Each two of the control gate lines have a wide spacing region having a large line-to-line width, a common connection region in which the two lines are connected in common in one line, and a narrow spacing region having a small line-to-line width. The wide spacing regions are disposed on both sides of the common connection region in the second direction. Since a comparatively large space can be secured on both sides of the common connection region in which two control gate lines are connected in common, the wide spacing regions of each two control gate lines adjacent thereto are disposed by utilizing the large space. The wide spacing region may be used as a contact region for other interconnects such as bit lines.
Since the common connection regions for which a large space is not needed are formed on both sides of the wide spacing region, it is unnecessary to increase the space for forming the wide spacing region. This eliminates the need to decrease the degree of integration in order to secure the wiring space for the control gate lines even if one memory cell has two trap sites, whereby a highly integrated nonvolatile semiconductor memory device can be provided.
The width of the common connection region may be larger than the width of each two of the control gate lines in the wide spacing region. This enables each two of the control gate lines to be connected with one of the sub control gate lines at the common connection region having a large width.
First and second wiring-only regions may be formed in the memory cell array region and separated from each other in the first direction. In the first wiring-only region, the common connection region may be connected to an even-numbered sub control gate line, and the wide spacing region may be connected to an odd-numbered sub control gate line. In the second wiring-only region, the common connection region maybe connected to an odd-numbered sub control gate line, and the wide spacing region may be connected to an even-numbered sub control gate line.
The arrangement pitch of the control gate lines can be minimized by disposing the common connection regions and the wide spacing regions in a zigzag arrangement.
The nonvolatile semiconductor memory device may further comprise: a plurality of bit lines disposed between each two of the control gate lines and formed of impurity layers extending in the first direction; and a plurality of sub bit lines which extend in the first direction in an upper layer of the bit lines and are connected to the bit lines, the number of the sub bit lines being equal to the number of the bit lines.
In this case, each of the bit lines may be divided into a plurality of bit split lines by a discontinuous region which faces the common connection region. Each of the sub bit lines may be connected to the bit split lines which make up one of the bit lines. This enables the bit lines divided in the first direction to be backed by the sub bit lines.
Each of the bit lines may have an enlarged region which faces the wide spacing region of each two of the control gate lines and have an increased line width. Each of the bit lines may be connected to the sub bit lines at the enlarged region. Since the discontinuous regions of the bit lines are provided on both sides of the enlarged region of the bit line, it is unnecessary to increase the pitch of the bit lines for forming the enlarged region, whereby the memory cells can be highly integrated.
The sub bit lines may make up a first metal interconnect layer, and the sub control gate lines may make up a second metal interconnect layer.
In this case, each of the bit lines may be connected to one of the sub bit lines through a contact formed in the enlarged region, and each two of the control gate lines may be connected with one of the sub control gate lines through a connection section formed in the common connection region. The connection section may include a contact, the island-like first metal interconnect layer, and a via.
The contact and the connection section may be substantially formed in a single line in the first direction. In this case, each of the sub bit lines avoids the connection section in order to prevent interference with the connection section.
The nonvolatile semiconductor memory device may further comprise: a select region disposed adjacent to the memory cell array region in the first direction; a plurality of main control gate lines extending in the first direction in the select region and the memory cell array region, the number of the main control gate lines being smaller than the number of the sub control gate lines; and a plurality of main bit lines extending in the first direction in the select region and the memory cell array region, the number of the main bit lines being smaller than the number of the sub bit lines. This enables the number of main bit lines and the number of main control gate lines to be decreased, whereby a surplus of wiring space is produced because the total number of interconnects decreases even if the main bit lines and the main control gate lines are disposed in the same layer.
Specifically, the main bit lines and the main control gate lines may make up a third metal interconnect layer.
In this case, the select region may include: a sub control gate select circuit which selectively connects the sub control gate lines with the main control gate lines; and a sub bit select circuit which selectively connects the sub bit lines with the main bit lines.
The select region may include first and second select regions disposed on both sides of the memory cell array region in the first direction. The degree of freedom relating interconnect is further increased by dividing the select region to which the sub bit lines and the sub control gate lines extend in two.
The first select region may include: a first sub bit select circuit which selectively connects one of an odd-numbered sub bit line and an even-numbered sub bit line with the main bit lines; and a first sub control gate select circuit which selectively connects one of an odd-numbered sub control gate line and an even-numbered sub control gate line with the main control gate lines. The second select region may include: a second sub bit select circuit which selectively connects the other of the odd-numbered sub bit line and the even-numbered sub bit line with the main bit lines; and a second sub control gate select circuit which selectively connects the other of the odd-numbered sub control gate line and the even-numbered sub control gate line with the main control gate lines.
Since the control gate select circuits can be dispersed in the first and second select regions in this manner, the circuit layout is facilitated.
A plurality of memory blocks each of which is formed of the memory cell array region and the first and second select regions disposed on both sides of the memory cell array region may be arranged in the first direction. This enables an increase in the storage capacity of the nonvolatile semiconductor memory device. Moreover, since the length of the sub control gate lines and the sub bit lines can be decreased, wiring capacitance can be reduced. Furthermore, since data can be collectively erased in the block unit, the erase unit can be reduced in comparison with the case of erasing data over the entire memory.
In this case, a main bit line driver which drives the plurality of the main bit lines may be provided on one end of the memory blocks arranged in the first direction.
This enables the main bit lines to be shared by the memory blocks, and the main bit line driver to be shared by the memory blocks.
In addition, a main control gate line driver which drives the plurality of the main control gate lines may be provided on the other end of the memory blocks arranged in the first direction.
This enables the main control gate lines to be shared by the memory blocks, and the main control gate line driver to be shared by the memory blocks.
A word line driver which drives a plurality of word lines may be provided on either side of the memory blocks in the second direction. In order to further increase the storage capacity of the nonvolatile semiconductor memory device, the memory blocks may be disposed on both sides of the word line driver in the second direction.
Each of the two nonvolatile memory elements may have an ONO film consisting of an oxide film (O), nitride film (N), and oxide film (O) as a charge trap site. However, other types of structures may be employed.